The present invention relates to a drive circuit.
There has been known a drive circuit of the push-pull type as shown in FIG. 1, as a drive circuit for driving a node accompanied by a large stray capacitance. The drive circuit is comprised of an E/D type inverter 2 for inverting an input signal VI and including a depletion type (D-type) MOS transistor TR2 and an enhancement type (E-type) MOS transistor TR4, and a push-pull circuit 4 containing D-type and E-type MOS transistors TR6 and TR8 whose current paths are connected in series between the power source terminals VD and VS. The input signal VI is applied to the gates of the MOS transistors TR4 and TR6. The output signal from the inverter 2 is supplied to the gate of the E-type MOS transistor TR8. A stray capacitor C1 is charged and discharged by the output signal from the push-pull circuit 4.
The drive circuit is superior to the inverter drive circuit of the E/D-type in that a DC current may be small and in that a large capacitor can be charged, although it has a relatively low power consumption, since the flow of a large charge current is allowed only during the switching transient time. In the drive circuit, the output stage is comprised of the E/D-type push-pull circuit, as described above. Because of this, the DC current flows through the push-pull circuit.
To prevent the generation of such DC current, an approach thus far proposed is a bootstrap buffer circuit of the static type using an E/E-type output circuit, as shown in FIG. 2, to allow a high level output signal to rise up to VD. The buffer circuit is formed of an inverter 2 for inverting an input signal VI comprised of a D-type MOS transistor TR2 and an E-type MOS transistor TR4, an output circuit 6 comprised of E-type MOS transistors TR12 and TR14 whose current paths are series-connected between the power source terminals VD and VS, and an E-type MOS transistor TR16 whose current path is coupled between the input terminal VI and the gate of the MOS transistor TR12. An output signal of the inverter 2 is supplied to the gate of the MOS transistor TR14 and a capacitor C2 is coupled between a node 8 between the MOS transistor TR12 and TR14 and the gate of the MOS transistor TR12.
In the buffer circuit, when the input signal VI goes to "1" level, the charging operation of the capacitor C2 starts. The charging operation continues until the input signal VI reaches a threshold voltage of the MOS transistor TR4 to render the MOS transistor TR4 conductive and the output signal from the inverter 2 falls below the threshold voltage of the MOS transistor TR14 to render the transistor TR14 nonconductive. When the MOS transistor TR14 is rendered nonconductive, the potential at the node 8 goes to "1" level, so that the potential at the other end of the capacitor C2 rapidly rises due to the bootstrap action. As a result, a voltage higher than the voltage VD is applied to the gate of the transistor TR12, and the power source voltage VD is supplied to the node 8 through the MOS transistor TR12. In other words, the potential at the node 8 rises up to the power source voltage VD. When the input signal VI goes to "0" level, a "1" level signal is generated from the inverter 2 to render the MOS transistor TR14 conductive and to discharge the capacitor C2. In this case, the MOS transistor TR12 is nonconductive and hence no stationary current flows in the output circuit 6. Therefore, the power consumption is reduced to an extremely small value.
In a static random access memory (RAM), 30 to 40% of the normal power consumption is consumed in a row decoder. Accordingly, for reducing the power consumption of the static RAM, it is very important to reduce the power consumption in the row decoder. For this reason, by using the boot strap circuit shown in FIG. 2, for example, for the row decoder buffer, the power consumption of the row decoder and thus of the overall RAM system can be limited to a small value.
Turning now to FIG. 3, there is shown a practical arrangement of a static type RAM using the bootstrap buffer circuit shown in FIG. 2 for the row decoder circuit. The static RAM is comprised of an address buffer circuit 10 for generating a row address signal, and an address decoding circuit 20 for decoding a row address signal derived from the address buffer circuit 10 to produce first and second output signals, and bootstrap type buffer circuits 30 and 40 for supplying a row selection signal to a memory matrix in response to the first and second output signals from the address decoding circuit 20. The address decoding circuit 20 is comprised of drive MOS transistors TR21 to TR2N coupled in parallel between a node N1 and a power source terminal VS, drive MOS transistors TR31 to TR3N coupled in parallel between a node N2 and the power source terminal VS, load transistors TR41 to TR4N coupled in series between the node N1 and a power source terminal VD, a load MOS transistor TR40 whose current path is connected to the node N2 at one end and to the node N1 through the MOS transistor TR41 at the other end. The gates of these MOS transistors are so connected as to receive an address signal from the address buffer circuit 10, the gates of these MOS transistors TR21 and TR31 are coupled with the gates of the MOS transistors TR40 and TR41, respectively, and the gates of the MOS transistors TR22 to TR2N are coupled with the gates of the MOS transistors TR32 to TR3N, respectively.
The buffer circuit 30 is formed of a first inverter for inverting a first output signal from the decoding circuit 20, which is formed of a D-type MOS transistor TR51 and an E-type MOS transistor TR52, a second inverter for inverting an output signal from the first inverter, which is formed of E-type MOS transistors TR53 and TR54, a capacitor C3 coupled between the gate of the MOS transistor TR53 and a node N3 of the MOS transistors TR53 and TR54, a MOS transistor TR55 having a current path connected between the gates of the MOS transistors TR52 and TR53, and a third inverter formed of E-type MOS transistors TR56 and TR57 having current paths serially coupled between the power source terminals VD and VS. The gates of these MOS transistors TR56 and TR57 are respectively coupled with the gates of the MOS transistors TR53 and TR54. A node N4 between the MOS transistors TR56 and TR57 is used as an output terminal of the buffer circuit 30 and is coupled with a word line WL1 of the memory matrix.
The buffer circuit 40, like the buffer circuit 30, is formed of MOS transistors TR61 to TR67 and a capacitor C4 which respectively correspond to the transistors TR51 to TR57 and the capacitor C3 in the buffer circuit 30. In the buffer circuit 40, a node N5 between the MOS transistors TR66 and TR67 is used as an output terminal from which an output signal corresponding to the second output signal from the address decoding circuit 20 is supplied to a word line WL2 of the memory matrix.
Assume now that a first output signal from the address decoding circuit 20, i.e. a potential at the node N1, is at "0" level. In this case the MOS transistor TR52 is kept nonconductive. As a result, the MOS transistors TR54 and TR57 are conductive, the capacitor C3 is kept in a discharge state, and a "0" level signal is produced from the output terminal N4. Then, a potential at the node N1 of the address decoding circuit 20 goes to "1" level, the capacitor C3 is charged through the MOS transistor TR55. Then the potential at the node N1 reaches the threshold voltage of the MOS transistor TR52 to render the MOS transistor conductive. At this time the MOS transistors TR54 and TR57 are nonconductive and the potentials at the nodes N3 and N4 abruptly rise to "1" level. Then the potential at the other end of the capacitor C3 or the gates of the MOS transistors TR53 and TR56 is abruptly risen to a voltage level above the voltage VD, through the bootstrap action, thereby setting the MOS transistors TR53 and TR56 completely conductive. As a result, the potentials at the nodes N3 and N4 are kept at the VD level. Therefore, the word line WL1 accompanied by a large stray capacitance can be driven satisfactorily.
For example, where the potential at the node N1 in the address decoding circuit 20 is shifted from "0" level to "1" level, an address signal AS2 changing from a high level to a low level, as shown in FIG. 4, is applied to gates of the MOS transistors TR21 to TR2N, and at the same time, an address signal AS1 changing from a low level to high level is applied to the gates of the MOS transistors TR41 to TR4N. Consequently, the MOS transistors TR21 to TR2N are nonconductive, the MOS transistors TR41 to TR4N are conductive, and the potential at the node N1 changes from "0" level to "1" level, as indicated by a broken line NP1.
In this type of row decorder circuit, a constant current flows only through the MOS transistors TR51 and TR52 in a selected buffer circuit, for example, the buffer circuit 30. Therefore, the power consumption of the decoder circuit is extemely small. When the output signal from the address decoding circuit 20, the potential at the nodes N1 and N2 is dull in its rise time characteristic, however, a proper bootstrap operation is not performed in the buffer circuits 30 and 40. When the rise time characteristic of the potential at the node N1 in the decoding circuit 20 is gentle, for example, the MOS transistor TR52 is rendered conductive before the capacitor C3 of the buffer circuit 30 is satisfactorily charged, so that the MOS transistor TR54 is rendered nonconductive, the potential at the node N3 rises and hence the gate potential of the MOS transistors TR53 and TR56 rises. However, since the capacitor C3 is insufficiently charged, an insufficient bootstrap action is obtained, the rise of the potential at the node N4 is gentle and the potential at the node N4 fails to rise up to the VD level. In order to obtain a proper bootstrap operation in the buffer circuits 30 and 40, it is necessary that the rise time characteristic of a drive signal for the MOS transistors TR40 to TR4N is made steep and the rise time characteristic of the output signal from the address decoding circuit 20 is made steep. To this end, it is necessary to enlarge the dimensions of the MOS transistors making up the address buffer circuit 10 for driving these MOS transistors TR40 to TR4N, increasing the power consumption in this circuit.